The explosive growth of cloud computing and AI – from generative, and reasoning, to (ultimately) agentic systems – is creating unprecedented demand for bandwidth, as the amount of data that must be moved both within and between data centers continues to surge. In turn, this exposes growing limitations in the underlying interconnects that not only span the data center fabric and rack level but also extend deep inside servers – down to where they link XPUs, memory, and other system components at the package and die level.
Copper-based (electrical) interconnects have long been the industry’s workhorse thanks to their low cost, simplicity, and reliability. Yet today, they are increasingly hitting fundamental limits: while highly energy-efficient electrical links can be realized, they are typically confined to very short reaches (on the order of millimeters). At longer distances and higher lane rates, power consumption rises sharply, thermal constraints intensify, and signal integrity degrades. In other words, electrical I/O is rapidly becoming a key barrier to scaling next-generation AI and machine learning systems.
Optical interconnects have emerged as a critical path forward. By transmitting data using light rather than electrical signals, they are far less sensitive to distance, enabling much better energy efficiency while mitigating many of the crosstalk and thermal challenges inherent to copper links. However, even optical technologies are now being pushed to new extremes – as the need emerges for (multi) terabit-per-second interfaces, ultra-high energy efficiency, and extremely low (sub-microsecond) latency.
Meeting these requirements will take more than incremental innovation. It calls for a fundamental rethinking of the optical interconnect roadmap; one that progressively brings optics closer to the silicon – from the front panel, into the package, and ultimately firmly integrated into the wafer stack.
Pluggable optics (PO): The longstanding – and still very much alive – workhorse
For more than two decades, pluggable optical transceivers have been the backbone of high-speed telecom and datacom networks – powering everything from enterprise workloads and video streaming to today’s hyperscale cloud infrastructure. Inserted into standardized ports on switches, routers, and servers, pluggables convert electrical signals from the host into optical signals for transmission over fiber – and back again on the receive side.
They deliver:
Modularity and flexibility – optics can be upgraded independently of the (electrical) host.
Serviceability – pluggables are hot-swappable, meaning they can be replaced without system downtime.
Multi-vendor interoperability – achieved via IEEE 802.3 standards, and through widely-adopted multi-source agreement (MSA) form factors such as QSFP, QSFP-DD, and OSFP.
Thermal stability – the optical engine sits in a front-panel cage, physically separated from the power‑dense ASIC; this helps protect lasers, modulators, and photodetectors from excessive heat (improving reliability).
Across successive generations, pluggable optical transceivers have scaled from 100/200G to 400G and 800G by pushing baud rates (the number of symbols transmitted per second on a single optical lane), adopting higher-order modulation (such as PAM-4), and increasing the number of parallel lanes.
And despite their maturity, pluggable optics continue to evolve. First-generation 1.6T pluggable transceivers, for instance – relying on 200Gbps per-lane data rates, combined in an eight-lane parallel architecture – are approaching sampling and early deployment, targeting direct-reach (DR) intra-data center links as well as forward-reach (FR) connections over single-mode fiber.
The key enabler is silicon photonics (SiPho), which underpins this scaling through a combination of (silicon-based) optical and electronic building blocks, including Mach–Zehnder modulators that play a central role in enabling cost-effective 200Gbps per-lane operation while keeping power consumption in check.
Looking further ahead, toward the end of the decade, the industry is eyeing the 3.2T pluggable optics milestone. Yet, achieving these performance levels will require continued advances in high-speed electronics, packaging, and thermal management – as well as a substantial expansion of the silicon photonics (SiPho) toolbox. On the transmit side, for instance, optical modulators will need to support bandwidths beyond 100GHz while maintaining low insertion loss and high modulation efficiency – requirements that are becoming increasingly difficult to meet with conventional silicon devices alone.
Fig. 1: Pluggable optics have delivered an order-of-magnitude leap in performance in the past few years – both in bandwidth density and power efficiency. Source: imec.
Addressing these limitations is driving interest in the heterogeneous integration of higher-performance electro-optic materials such as lithium niobate (LiNbO₃) and lithium tantalate (LiTaO₃). Techniques such as micro-transfer printing offer a promising path to integrate these materials onto silicon photonics platforms. Early results are encouraging, but further research is ongoing to scale these approaches to high-volume manufacturing – so that future 3.2T modules can be built with the same practicality, reliability, and cost discipline that made pluggable optics the industry’s workhorse in the first place.
In parallel, alternative scaling approaches are also being explored. Concepts such as extreme pluggable optics (XPO) target capacities up to 12.8T by further increasing bandwidth density, albeit at the expense of significantly higher system complexity and the need for liquid cooling, which – at least for now – impacts both cost and practical deployment.
A double world-first: Integrating LiNbO₃ and LiTaO₃ on SiPho via micro-transfer printing
As optical interconnects (need to) push beyond today’s 200Gbps-per-lane standard, GeSi-based devices increasingly struggle to deliver the required combination of bandwidth and energy efficiency. While GeSi modulators have demonstrated scaling to 400Gbps per lane in the C-band, such performance has not yet been achieved in the O-band. To unlock the next performance leap in pluggable optical interconnects, researchers are therefore investigating the heterogeneous integration of advanced electro-optic materials – such as lithium niobate (LiNbO₃) and lithium tantalate (LiTaO₃) – onto silicon photonics, paving the way for a new class of high-speed modulators and photodetectors.
A promising enabler is micro-transfer printing, which enables the precise placement of thin-film materials onto SiPho wafers without the material waste, post-bonding complexity, and cost typically associated with conventional wafer bonding. Two world-first results highlight its potential:
First, researchers from imec and Ghent University showcased an O-band 320Gbps unamplified optical link over 2km of single-mode fiber. This was achieved using a high-bandwidth 100GHz germanium photodiode in combination with transfer-printed thin-film lithium niobate Mach-Zehnder modulators (MZMs), integrated onto a SiPho platform and co-packaged with custom-designed traveling-wave drivers and TIAs. This work marked the first seamless integration of LiNbO₃ modulators onto a silicon photonics platform using micro-transfer printing.
Fig. 2: The first seamless integration of LiNbO₃ modulators onto a silicon photonics platform using micro-transfer printing. Source: imec.
The team also achieved the first-ever heterogeneous integration of a LiTaO₃ modulator on a silicon photonic integrated circuit. Using the same micro-transfer printing technique previously applied to lithium niobate, the researchers achieved full compatibility with the entire wafer stack, enabling co-integration with other photonic building blocks such as heaters, filters, and germanium photodetectors without compromising their performance.
While these modulators are still relatively large, they offer a viable path for further scaling pluggable transceivers, where footprint constraints are less stringent. At the same time, alternative device concepts are being explored to meet the tighter size and integration requirements of future co-packaged optics. These include compact, ultra-high-speed GeSi-based modulators operating in the C-band, as well as emerging approaches based on the integration of III-V materials into silicon photonics platforms.
Further work is required to scale these heterogeneous integration approaches to high-volume manufacturing. Nevertheless, the results highlight a promising route toward integrating >100GHz electro-optic devices on SiPho – a capability widely seen as essential for future 3.2T pluggable modules and next-generation optical interconnects supporting AI-driven infrastructure.
Fast-and-narrow co-packaged optics (CPO): A key pillar of the optical interconnect roadmap
Pluggable optics, however, are not the answer to every challenge. The rapid rise of (generative) AI workloads is pushing optical (inter)connectivity ever deeper into compute servers and accelerator clusters – all the way down to the chip-to-chip level.
At this scale, a new set of constraints emerges. Pluggable optical transceivers rely on very high baud rates, in combination with sophisticated digital signal processing (DSP) to compensate for signal degradation. While this works well at the rack or data center level, the power consumption and latency associated with heavy DSP become increasingly problematic for short-reach, chip-to-chip optical interconnects in AI and machine learning systems. Instead, they require intrinsically clean optical channels with extremely low bit-error rates, allowing each lane to operate without excessive equalization or DSP overhead.
This shift is precisely what drives the adoption of fast-and-narrow co-packaged optics (CPO). In a CPO system, the optical components are placed in close physical proximity to the (switching) silicon or compute die, shrinking the electrical path from several centimeters (as in pluggables) to just a few millimeters – or even less. By moving the electro-optic conversion point directly adjacent to the ASIC (within the same package), CPO greatly improves signal integrity, minimizes electrical losses, and reduces latency – without relying on power-hungry DSP. This makes CPO a compelling architecture for scaling next-generation AI and high-performance compute systems.
Fig. 3: Co-packaged optics shorten the electrical path between the optical engine and the host IC, enabling higher bandwidth density and eliminating the need for digital signal processing, thereby improving power efficiency. Source: imec.
But as early CPO deployments begin to emerge, integration complexity remains one of the defining challenges of the technology. Unlike pluggable optics – where the optical module is (largely) self-contained – CPO requires tight co-design and co-optimization, including photonic integrated circuits (PICs), electronic ICs (EICs), switch ASICs, fiber‑coupling strategies, thermal management, and advanced packaging. Addressing this multidisciplinary challenge is a central objective of imec’s Optical Interconnect Program.
In the CPO domain (also referred to as OIO2.5D), imec’s key research targets include:
Scaling optical engine capacity from 1.6T and 3.2T, toward 6.4T and ultimately 12.8T.
Enabling fast-and-narrow 400Gbps lane rates, and achieving bandwidth densities approaching 1Tbps per millimeter.
Facilitating energy efficiencies up to 5pJ/bit, trending toward 3pJ/bit in future technology generations.
Integrating the full optical stack – modulators, photo detectors, couplers, fiber attach, and thermal solutions – within a manufacturable package.
Reaching these targets depends heavily on advanced semiconductor packaging technologies that support dense integration of photonic and electronic components – think of 2.5D interposer architectures, through-silicon vias (TSVs), fan-out wafer-level packaging (FO-WLP), and (increasingly) 3D integration enabled by hybrid bonding – as well as the use of advanced (III-V) materials.
And then there’s the light source. While the long-term goal is to integrate lasers directly on the photonic chip, early CPO systems will still rely on externally mounted laser sources. This approach simplifies thermal management and mitigates long-standing reliability concerns of operating lasers near hot ASICs. The trade-offs: higher output power to compensate for optical losses, greater packaging complexity, and the need for additional fibers and connectors to route light into the package.
Realizing the first net-400Gbps per-lane transmission with a silicon-based EAM
In October 2025, imec announced a major advance for next‑generation optical interconnects: a beyond-110GHz C-band GeSi electro-absorption modulator (EAM) delivering a net data rate of 400Gbps per lane.
Leveraging the Franz-Keldysh effect, the device combines compact size, high speed, and low power consumption. And thanks to its GeSi foundation, it integrates seamlessly on 300mm CMOS-compatible SiPho platforms, offering a clear route to high-volume manufacturability.
This breakthrough reflects more than a decade of coordinated progress at both the device and system levels. On the device side, imec optimized footprint, doping schemes, and epitaxial growth processes. At the system level, a robust PAM-4 IM/DD transmission setup validated sustained net-400Gbps per-lane operation, demonstrating the practical readiness of GeSi EAM technology for future high-lane-rate optical engines.
3D integrated optics (OIO3D): The next frontier
As AI and machine learning systems scale to thousands of tightly interconnected accelerators, each linked to high-bandwidth memory stacks and peer processors over distances of only a few millimeters, the demands placed on optical interconnects become even more extreme. Over the next decade, they are expected to support bandwidth densities approaching (and surpassing) 10Tbps/mm, energy efficiencies well below 1pJ/bit, and ultra-low latencies (<100ns). These targets extend beyond what even advanced CPO architectures can achieve.
To meet these requirements, optics must move beyond the package and into the wafer stack itself. This is the foundation of 3D integrated optics. By collapsing the electrical path to micrometer-scale distances, OIO3D enables ultra-short, high-bandwidth, and energy-efficient optical links that make dense chip-to-chip optical fabrics feasible.
Fig. 4: By collapsing the electrical path to micrometer-scale distances, OIO3D enables ultra-short, high-bandwidth, and energy-efficient optical links that make dense chip-to-chip optical fabrics feasible. Source: imec.
Realizing 3D integrated optics requires overcoming several major technology challenges. These include scalable laser integration, the development of high-efficiency, high-bandwidth electro-optic components (e.g., based on GeSi, lithium niobate, lithium tantalate, indium phosphide, or barium titanate), and robust thermal management in densely stacked environments. Equally crucial are ultra-precise bonding and alignment techniques at wafer scale.
OIO2.5D vs OIO3D
An evolutionary step beyond CPO, OIO2.5D combines high‑density photonic integration with manageable packaging complexity by placing photonic and electronic dies side‑by‑side on a shared silicon interposer. Photonic layers are integrated using die‑to‑wafer Cu‑based hybrid bonding, a technique that enables ultrashort, low‑parasitic electrical paths.
This architecture initially targets optical engines in the 8-32Tbps range. It leverages 32-64 Gbps per‑lane rates, optimized for low‑power, DSP‑free operation to minimize latency and heat. Wavelength‑division multiplexing (8-32 wavelengths per fiber) further boosts aggregate bandwidth without increasing fiber count. The technology roadmap aims for bandwidth densities of 2Tbps per millimeter and energy efficiencies near 2 pJ/bit.
OIO3D represents the most advanced and ambitious vision for optical interconnects. Here, photonic layers are stacked directly above or below the compute silicon, creating a true chip‑scale optical fabric that collapses electrical paths to micrometer‑scale distances.
This approach relies on both die‑to‑wafer and wafer‑to‑wafer hybrid bonding, enabling extremely fine‑pitch vertical interconnects. With this level of vertical integration, OIO3D aims to extend bandwidth capabilities to tens of terabits per second (and beyond), while targeting energy efficiencies around 2 pJ/bit – with a longer‑term trajectory toward sub‑pJ/bit operation.
A key research vector is on‑wafer laser integration, using heterogeneous III‑V approaches such as quantum‑dot GaAs‑on‑Si. This is actively being explored within the EU Chips Act pilot lines for future large‑scale photonic systems.
Integration of barium titanate on a 300mm SiPho platform
In January 2026, Veeco Instruments Inc. and imec announced a 300mm high-volume-manufacturing-compatible process for integrating barium titanate (BaTiO3, BTO) on silicon photonics.
With exceptional electro-optic properties, BTO enables high-speed, low-power modulators for applications ranging from optical transceivers to quantum photonics, LiDAR, and AR/VR. Historically, however, bringing BTO to silicon at scale has been difficult due to cost, uniformity, and manufacturability constraints.
Leveraging a collaboration with imec, Veeco recently delivered its first molecular beam epitaxy (MBE) cluster system tailored for 300mm wafers. The platform supports the growth of single-crystalline BTO thin films on silicon – using solid and hybrid MBE – improving repeatability, material quality, and cost of ownership compared with conventional MBE solutions.
A look at timelines
Looking across the evolution of optical interconnects, it is clear the different approaches are progressing along different timelines.
Pluggable optics, already deployed at global scale, are entering a phase dominated by incremental technical optimizations rather than fundamental breakthroughs. Their roadmap continues – toward 1.6T and 3.2T modules – and pluggables will remain competitive for many use cases while new architectures ramp up.
Co-packaged optics are also approaching a stage of (relative) maturity. Key building blocks are transitioning into pilot-line support, supply-chain preparation, and wafer-level services – even as the industry continues to pursue higher bandwidth, faster lane rates, and better energy efficiency. The start of broad, large-scale CPO deployments is expected from 2027/2028 onward.
3D integrated optics remain in an earlier R&D stage. Current efforts focus on pathfinding and building the device/integration toolbox. First proof-of-concept demonstrators are anticipated within three to five years, with wider commercialization expected on a five- to ten-year horizon.
Bringing next-generation optical interconnects to market
Through its optical interconnects research program, imec develops the key building blocks for future optical transceivers, anticipating market needs years before commercial deployment.
Imec’s strength lies in being a true one-stop R&D environment, bringing together expertise in silicon photonics, advanced CMOS, 3D integration, materials research, and system-level modeling. This breadth allows researchers to explore novel concepts far more rapidly than is possible in high-volume manufacturing settings, enabling short development cycles, and the freedom to pursue unconventional (integration) approaches. The program is further strengthened by imec’s cross-technology optimization (XTCO) strategy, which drives scaling across technology domains.
A critical accelerator is the close collaboration between imec’s optical interconnect research teams and IC-Link, imec’s semiconductor manufacturing pillar. While imec’s early‑stage research focuses on pathfinding and prototyping, IC‑Link helps bring technologies toward higher technology‑readiness levels by refining process flows, improving manufacturability, establishing test strategies, and engaging the broader supply chain. Through IC-Link, industrial partners can also access and evaluate these technologies via imec’s 200mm and 300mm iSiPP silicon photonics platforms, providing a pathway from early-stage innovation to industrial deployment.
Beyond IC-Link, imec maintains close engagement with industrial partners through a variety of collaboration models. These span guided projects (in which imec and its partners jointly explore emerging technologies), to targeted bilateral programs (driven by partner-specific requirements), all the way to long-term core partner engagements. In parallel, imec collaborates closely with equipment suppliers, enabling early validation of advanced tools and process capabilities – well before they enter commercial use.
Together, these interactions ensure that imec’s optical interconnect research stays firmly grounded in real‑world system requirements, while accelerating the translation of advanced technologies into market-ready solutions.
Peter Ossieur received the M.Sc. degree in electrical engineering from Ghent University, Belgium in 2000, and the PhD degree in electrical engineering from the same university in 2005. From 2005 till 2009 he was a postdoctoral researcher at Ghent University, after which he joined Tyndall National Institute, where he became senior staff researcher. His research interests included electronic integrated circuit design and optical transmission systems. In 2017, he joined imec-IDlab, an imec embedded group at Ghent University. Today, he is director for XTCO Fabric and Optical Interconnect at imec, and holds a parttime appointment as professor at Ghent University. Peter Ossieur is a member of the ISSCC wireline subcommittee.
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