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빌드-어-칩-벤치 소개: 워크로드 사양부터 GDS까지

오픈소스 도구와 오픈소스 PDK를 활용해, 워크로드 사양부터 GDS 레이아웃에 이르기까지 AI 에이전트의 성능을 평가하여 칩 설계 워크플로우를 완료하는 능력을 검증합니다. “Build-A-Chip-Bench 소개: 워크로드 사양에서 GDS까지”라는 글은 Semiconductor Engineering에 처음 게재되었습니다.

번역이 완료되지 않아 원문을 표시합니다.

Existing chip design benchmarks test isolated steps, such as writing RTL from a specification, and are increasingly saturated. ChipAgents is developing Build-A-Chip-Bench with contributions from Nvidia to the benchmark suite and scoring rubric. The benchmark evaluates AI agents from workload specification through GDS layout, using open-source tools and an open-source PDK to assess their ability to complete the chip-design workflow. Each design must pass a hard gate, covering functional correctness against a hidden verification IP as well as routability, hold timing, and DRC, and designs that pass are scored on PPA against the task’s constraints. The best agent passes the hard gate on 65% of tasks and reaches an overall score of 16.6%. Frontier agents struggle to revisit earlier decisions, protect working behavior while optimizing, and plan around slow tool runs.

Read more here.

The post Introducing Build-A-Chip-Bench: From Workload Specification to GDS appeared first on Semiconductor Engineering.

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