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2026-10-27

llama.cpp releases23:27

b11933

vulkan: fix CI llvmpipe by allowing dim 3 broadcast in MUL_MAT (#31239) * vulkan: allow dim 3 broadcast in MUL_MAT supports_op rejected every MUL_MAT whose src0 and src1 differ in ne3, although mul_mm, mul_mmq and mul_mat_vec already broadcast src0 over dim 3 through broadcast3. Such a matmul then ran on the CPU with a copy of the weight, and the split layout changed with the number of streams in the ubatch. Keep the strict check for MUL_MAT_ID only, and route the broadcast cases away from mul_mat_vec_nc, the one path that requires equal ne3. * tests : harden MUL_MAT with permuted dim 3 broadcast cases Harden the MUL_MAT coverage with a weight broadcast over dim 3 against a permuted per-stream activation, the shape of an MLA output projection with a non unified KV cache, for a single token

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arXiv cs.DC12:00

When and Why to Use TMA: A Workload-Grounded Characterization of Tensor Memory Acceleration on NVIDIA Hopper GPUs

arXiv:2610.34907v1 Announce Type: new Abstract: The Tensor Memory Accelerator (TMA), introduced on NVIDIA Hopper, is used pervasively in production GPU kernels yet its usage is conspicuously selective: expert kernel developers in CUTLASS, FlashAttention-3, and FlashInfer apply TMA to some tensor operands within a kernel but fall back to cp.async, direct global loads, or distributed shared memory (DSM) for others. Vendor documentation describes the API, and recent microbenchmarking work characterizes TMA throughput in isolation, but neither answers the question practitioners actually face: given a memory operand in a kernel, should it use TMA, and if so, with or without cluster multicast? We address this gap with a workload-grounded characterization study on H100. We catalog the TMA, multic

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2026-10-26

SiliconANGLE AI23:58

Marvell’s early chipmaking gamble pays off amid AI demand

Eight years ago, chipmaker Marvell Technology Inc. decided to play leapfrog with nanometers, and its trajectory has been steadily upward since. In semiconductor manufacturing, nanometer designations identify generations of chipmaking technology, known as process nodes, rather than the exact physical dimensions of transistors. Advanced process nodes generally enable greater transistor density and improvements in performance […] The post Marvell’s early chipmaking gamble pays off amid AI demand appeared first on SiliconANGLE.

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2026-10-21

AWS Machine Learning Blog05:14

i14 releases the Laplace 3B linear attention model: inference with fixed-state memory, implemented on AWS Trainium2 and native PyTorch.

i14 has launched the Laplace 3B model with 3.028 billion parameters, which replaces Softmax attention with Gated Linear Attention (GLA). During inference, its per-sequence recursive state remains constant at 29.5 MB, independent of context length. The model was trained and validated on a single AWS trn2.48xlarge instance (equipped with 16 Trainium 2 chips), achieving a training throughput of 120,000 tokens per second and an inference throughput of 11,544 output tokens per second (with 1,280 concurrent sequences). All performance metrics are based on internal measurements conducted by i14 and the AWS GenAIIC team.

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