Qwen-3.8-27B-ROCmFP4-FAST-GGUF
This repository contains optimized **ROCmFP4** and **ROCmFP8** GGUF releases of **Qwen 3.8 27B**, custom-engineered for **AMD Strix Halo (Ryzen AI Max+ 395 / Radeon 8060S)** and **AMD Radeon discrete GPUs**. > ๐ ๏ธ **Unified HaloFPX Server:** github.com/julianmb/halofpx (Multi-model zoo, hot-swapping, OpenAI API) > ๐ **Qwen 3.8 Dedicated Deep-Dive:** github.com/julianmb/q38rocm (Standalone optimization report, benchmarks & tuning) Strix Halo features a **50 TOPS XDNA 2 NPU** (`/dev/accel/accel0`). Extensive empirical benchmarking demonstrates: - **Sustained Decode Ceiling:** **33.8 tok/s** via embedded MTP (iGPU only) is the practical ceiling. The NPU does *not* improve sustained decode speed. - **Proven NPU Value:** **1.8ร faster first-token TTFT on long prompts (870 ms vs 1587 ms)** via hybrid NPU-burst โ iGPU handoff (`scripts/run_pipeline.py`). - **See `docs/NPU_INTEGRATION.md`** for complete setup instructions.
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This repository contains optimized **ROCmFP4** and **ROCmFP8** GGUF releases of **Qwen 3.8 27B**, custom-engineered for **AMD Strix Halo (Ryzen AI Max+ 395 / Radeon 8060S)** and **AMD Radeon discrete GPUs**. > ๐ ๏ธ **Unified HaloFPX Server:** github.com/julianmb/halofpx (Multi-model zoo, hot-swapping, OpenAI API) > ๐ **Qwen 3.8 Dedicated Deep-Dive:** github.com/julianmb/q38rocm (Standalone optimization report, benchmarks & tuning) Strix Halo features a **50 TOPS XDNA 2 NPU** (`/dev/accel/accel0`). Extensive empirical benchmarking demonstrates: - **Sustained Decode Ceiling:** **33.8 tok/s** via embedded MTP (iGPU only) is the practical ceiling. The NPU does *not* improve sustained decode speed. - **Proven NPU Value:** **1.8ร faster first-token TTFT on long prompts (870 ms vs 1587 ms)** via hybrid NPU-burst โ iGPU handoff (`scripts/run_pipeline.py`). - **See `docs/NPU_INTEGRATION.md`** for complete setup instructions.
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